1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to dynamic random access memory (DRAM) devices of the type employing one-transistor memory cells. The invention also relates to NAND type DRAM devices including in each cell section a plurality of series-connected one-transistor memory cells associate with a corresponding bit line.
2. Description of the Related Art
Dynamic random access memory (DRAM) devices become more widely used in the manufacture of digital equipments, such as small-size computers, as the speed and cost advantages of the devices are further enhanced. The cost for each bit using DRAMs has gone down as the number of bits or memory cells per package goes up. As the number of bits increases, the cell size decreases, the magnitude of the storage capacitor in each cell of necessity decreases. This factor may reduce the reliability of data storage in each of DRAM devices, which are strongly demanded to attain a higher packing density on a chip substrate of limited size.
In recent years, in order to satisfy the "higher integration-density" requirements, what is called the "trench-type" DRAM devices have been proposed by some leading semiconductor manufacturers. One of the highly advanced trench-type DRAM devices typically includes a plurality of rectangular prism-shaped grooves (called "trenches") that are formed in the top surface of a semiconductor substrate. Each of the trenches permits the formation of a capacitive element (capacitor) for data storage included in one of a plurality of rows and columns of memory cells in such a manner that an individual capacitor electrode of each element is insulatively buried in a corresponding one of the trenches while it faces the inner wall of the trench to provide a preset storage capacitance Cs. The capacitor electrode is referred to as a "storage node" in the art of semiconductor memory devices. The substrate is coupled to a plate voltage Vp and functions as the other capacitor electrode that is commonly used for all of the capacitors, that is, a common electrode.
With such a "trench-type cell" structure, it may be possible to attain a maximally increased storage capacitance Cs within a narrow one-cell area on the substrate. However, when an attempt is made to cope with a further improved integration density in recent years, even such a trench-cell structure suffers from the following problems: the difficulty in formation of the trench, and the degradation in the charge-storage reliability of metal oxide semiconductor (MOS) transistors.
Regarding the difficulty in formation of the trench, the trench must be formed more deeply to attain a desired storage capacitance Cs if the trench cell is further miniaturized in size (particularly, opening area) with the further improvement of the integration density of DRAM devices. As the trench is formed more narrowly and deeply, the manufacturing process for the trench becomes more difficult, thereby lowering the yield of production.
Regarding the degradation of reliability, as the memory size decreases, a MOS transistor contained in each cell and acting as a data-transfer gate is miniaturized, thus causing the channel region to decrease in length. The channel length reduction gives bad influences such as generation of punch-through in the MOS transistor and reduction in the threshold voltage Vth. Such phenomenon is known as the "short channel" effect in the semiconductor memory art. As a result, the cut-off characteristic of the MOS transistor is extremely deteriorated. Also, the operating reliability of DRAM devices is lowered.
Further, stress tends to occur in the semiconductor substrate. Occurrence of the stress makes it easier to generate a junction leak, which makes it difficult to hold charges on the cell capacitor for a long period of time. This is also a serious bar to the maintenance of an improved operation reliability of highly integrated DRAM devices.